(1) Field of the Invention
The present invention relates to a method for making metal plugs in via holes for multilevel inter-connections, and more particularly relates to a method for making buried metal plugs for stacked vias for integrated circuits on semiconductor substrates without destroying the mask alignment marks in the kerf area (the area between chips on the substrate) and without requiring additional masking steps.
(2) Description of the Prior Art
The packing density of devices on integrated circuits has dramatically increased on ultra-large scale integrated (ULSI) circuits due to advances in semiconductor processing, such as the use of high-resolution photolithography and anisotropic plasma etching. In this sub-micron technology the packing density of devices on integrated circuits is strongly dependent on the metal interconnection density. Therefore, the design rules are more aggressively scaled, and in addition more levels of metal are added to effectively interconnect the high density of discrete devices on the chip.
One method of achieving these high-density metal interconnections is to form stacked vias between the various levels of metal interconnections. In addition, because of the high photoresist resolution, it is necessary to form a planar surface due to the need to use a shallower depth of focus (DOF) when exposing the photoresist. This has necessitated the use of metal plugs in the contact openings to devices on the semiconductor substrate, and to the use of metal plugs in via holes between various levels of metal interconnections to replace the non-filled via holes used in the past, in which the top metal layer conformally fills the via holes resulting in a non-planar structure. Also it is more difficult to achieve good step coverage in the smaller via holes having high aspect ratios.
The metal plugs in via holes are formed by conformally depositing a metal, such as tungsten (W), that completely fills the via holes. The tungsten is then etched back or chemical/mechanically polished (CMP) back to the surface of an insulating layer that has the via holes between the patterned metal levels, or to the insulating layer in which the contact openings are formed over the devices on the substrate.
Unfortunately, there are several problems associated with completely etching back or chem/mech polishing back the tungsten to the insulating surface. For example, when the tungsten (W) layer is chem/mech polished back to globally planarize the surface of the substrate, the alignment marks are filled with tungsten in the kerf areas. When the next level of metal is deposited, the alignment marks in the kerf areas are no longer visible during the subsequent alignment of the reticle (mask) used during the exposure of the photoresist in the step-and-repeat tool for patterning the next level of metal. This problem is depicted in FIGS. 1-3. FIG. 1 shows the alignment mark 2 in one of the kerf areas on a substrate having an insulating layer 10, with a first titanium/titanium nitride (Ti/TiN) barrier layer 12, and a tungsten layer 14. FIG. 2 shows the kerf area filled with tungsten 14 after chem/mech polishing back. Now as shown in FIG. 3, when the next level of metal (e.g., AlCu) is deposited, the surface is essentially planar and the alignment mark 2 is undetectable, and the next photomask level cannot be aligned for patterning the next level of metal interconnections. Another problem with CMP is depicted in FIG. 4. When the tungsten is polished back, residual tungsten 3 remaining on the beveled edges of the wafer (substrate) 5 can peel and result in contamination that can cause defects on the chips during subsequent processing.
Alternatively, to avoid the CMP problems, a plasma etch-back process can be used to etch back the tungsten to form the metal plugs in the via holes, while providing visible alignment marks in the kerf area. However, this can also result in several undesirable effects, as depicted in FIGS. 5-7. A typical via hole 4 etched in the insulating layer 10 is shown in FIG. 5 having the Ti/TiN first barrier layer 12, and filled with tungsten 14, making contact to the underlying conducting layer 8, such as one of the levels of interconnecting metallurgy, or in the case of forming the contact to the devices on the substrate, to one of the electrically conductively doped polysilicon layers. When the tungsten is etched back to the Ti/TiN surface 12, as shown in FIG. 6, the rough topography of the tungsten layer 14 can result in a rough surface 7 on the Ti/TiN barrier layer and also leaves identical tungsten residue 7 on the plug 14', and on the surface of the Ti/TiN if a tungsten overetch is not used. The residual tungsten is undesirable and can cause defects. Typically the overetch, as shown in FIG. 7, also results in undesirable recessing of the plug 14' in the via hole or contact opening, and results in a non-planar surface for the next level of metal 18, which includes a second barrier layer 16, over the metal plug 14' in the via hole 4. This can make it difficult to form plug contacts to the substrate as well as stacked vias over the contact structures.
Various methods for making metal contact plugs (studs) on integrated circuits have been reported. Dalal et al. U.S. Pat. No. 5,434,451, describe a method using a tungsten liner process for simultaneously forming contact studs and interconnect lines. Another method that teaches the formation of metal plugs and/or wiring metal layers is described by Hayakawa et al. in U.S. Pat. No. 5,502,008. Their method uses a chemical/mechanical polish (CMP) to flatten the metal plugs prior to etching. Still another method is described by Doan et al., U.S. Pat. No. 5,514,245, utilizing two CMPs, one with a low compressibility, and one with a soft compressible pad to remove microscratches. Another method that uses a two-step CMP is described in U.S. Pat. No. 5,244,534. Another method for removing dielectric layers from over an alignment mark is described by Caldwell in U.S. Pat. No. 5,401,691.
There is still a need in the semiconductor industry to provide an improved process for making metal plugs for stacked via hole over contact openings which do not requiring extra masking steps to expose the alignment marks for aligning. And still a need to provide a contamination-free process that provides a planar structure.